1. A finite-state machine (FSM) or simply a state machine is used to design both computer programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of user-defined states. The machine is in only one state at a time; the state it is in at any given time is called the current state.
2. Dec 23, 2015 The Finite State Machine. The system to be designed is a very simple one and its purpose is to introduce the idea of converting a FSM into VHDL. This FSM has four states: A, B, C, and D. The system has one input signal called P, and the value of P determines what state the system moves to next. The system changes state from A to B to C to D as.

1. 4 Bit Serial Adder
2. Vhdl Code For Serial Adder Using Finite State Machine Design
3. Vhdl Code For Serial Adder Using Finite State Machines
4. Parallel Adder
5. Vhdl Code For Serial Adder Using Finite State Machine Programming

State Machines

Assume that i want to add 4 signals a,b,c,d and i want to add them using adder2 which adds to signals only.and i want to implement them in adder tree format so in the first state a, and b will be added and saved at signal y and c and d will be added as well and saved at signal z then in the next state y and z will be added and and the result will be at the the output x. Index Terms — VHDL code, Verilog code, finite state machine, Mealy machine, Moore machine, modeling issues, state encoding. INTRODUCTION The automata theory is the basis behind the traditional model of computation and is used for many purposes other than controller circuit design, including computer program.

XST proposes a large set of templates to describe Finite State Machines (FSMs). By default, XST tries to recognize FSMs from VHDL/Verilog code, and apply several state encoding techniques (it can re-encode the user's initial encoding) to get better performance or less area. However, you can disable FSM extraction using a FSM_extract design constraint.

Please note that XST can handle only synchronous state machines.

There are many ways to describe FSMs. A traditional FSM representation incorporates Mealy and Moore machines, as in the following figure:

For HDL, process (VHDL) and always blocks (Verilog) are the most suitable ways for describing FSMs. (For description convenience Xilinx uses 'process' to refer to both: VHDL processes and Verilog always blocks).

You may have several processes (1, 2 or 3) in your description, depending upon how you consider and decompose the different parts of the preceding model. Following is an example of the Moore Machine with Asynchronous Reset,'RESET'.

• 4 states: s1, s2, s3, s4
• 5 transitions
• 1 input: 'x1'
• 1 output: 'outp'

This model is represented by the following bubble diagram:

Related Constraints

Related constraints are:

• FSM_extract
• FSM_encoding
• FSM_fftype
• ENUM_encoding

FSM with 1 Process

Please note, in this example output signal 'outp' is a register.

VHDL

Following is the VHDL code for an FSM with a single process.

Verilog

Following is the Verilog code for an FSM with a single process.

FSM with 2 Processes

To eliminate a register from the 'outputs', you can remove all assignments 'outp <=...' from the Clock synchronization section.

This can be done by introducing two processes as shown in the following figure.

VHDL

4 Bit Serial Adder

Following is VHDL code for an FSM with two processes.

Verilog

Following is the Verilog code for an FSM with two processes.

FSM with 3 Processes

You can also separate the NEXT State function from the State Register:

Separating the NEXT State function from the State Register provides the following description:

VHDL

Following is the VHDL code for an FSM with three processes.

Verilog

Following is the Verilog code for an FSM with three processes.

State Registers

State Registers must to be initialized with an asynchronous or synchronous signal. XST does not support FSM without initialization signals. Please refer to the 'Registers' section of this chapter for templates on how to write Asynchronous and Synchronous initialization signals.

In VHDL the type of a state register can be a different type: integer, bit_vector, std_logic_vector, for example. But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type.

In Verilog, the type of state register can be an integer or a set of defined parameters. In the following Verilog examples the state assignments could have been made like this:

These parameters can be modified to represent different state encoding schemes.

Next State Equations

Next state equations can be described directly in the sequential process or in a distinct combinational process. The simplest template is based on a Case statement. If using a separate combinational process, its sensitivity list should contain the state signal and all FSM inputs.

FSM Outputs

Non-registered outputs are described either in the combinational process or concurrent assignments. Registered outputs must be assigned within the sequential process.

FSM Inputs

Registered inputs are described using internal signals, which are assigned in the sequential process.

State Encoding Techniques

XST supports the following state encoding techniques.

• Auto
• One-Hot
• Gray
• Compact
• Johnson
• Sequential
• User

Auto

In this mode XST tries to select the best suited encoding algorithm for each FSM.

One-Hot

One-hot encoding is the default encoding scheme. Its principle is to associate one code bit and also one flip-flop to each state. At a given clock cycle during operation, one and only one state variable is asserted. Only two state variables toggle during a transition between two states. One-hot encoding is very appropriate with most FPGA targets where a large number of flip-flops are available. It is also a good alternative when trying to optimize speed or to reduce power dissipation.

Gray

Gray encoding guarantees that only one state variable switches between two consecutive states. It is appropriate for controllers exhibiting long paths without branching. In addition, this coding technique minimizes hazards and glitches. Very good results can be obtained when implementing the state register with T flip-flops.

Compact

Compact encoding, consists of minimizing the number of state variables and flip-flops. This technique is based on hypercube immersion. Compact encoding is appropriate when trying to optimize area.

Johnson

Like Gray, Johnson encoding shows benefits with state machines containing long paths with no branching.

Sequential

Sequential encoding consists of identifying long paths and applying successive radix two codes to the states on these paths. Next state equations are minimized.

User

In this mode, XST uses original encoding, specified in the HDL file. For example, if you use enumerated types for a state register, then in addition you can use the enum_encoding constraint to assign a specific binary value to each state. Please refer to the 'Design Constraints' chapter for more details.

Log File

Vhdl Code For Serial Adder Using Finite State Machine Design

The XST log file reports the full information of recognized FSM during the macro recognition step. Moreover, if you allow XST to choose the best encoding algorithm for your FSMs, it will report the one it chose for each FSM.

... Synthesizing Unit <fsm>. Related source file is state_machines_1.vhd. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 1 | | Reset type | asynchronous | | Encoding | automatic | | State register | D flip-flops | ---------------------------------------------------------- ... Summary: inferred 1 Finite State Machine(s). ... Unit <fsm> synthesized. HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 1 1-bit register : 1 ... Optimizing FSM <FSM_0> with One-Hot encoding and D flip-flops. ... ...

Finite state machine is a graphical model/representation of sequential activities or events. After representing and modeling the events they can be implemented easily in case of sequential logic designs. Finite state machines can be utilized in many fields of study e.g neural networks, artificial intelligence, mathematics, games, robotics and sequential flow of data. Since we are dealing with the sequential circuits so i will explain their use in sequential circuit design in this tutorial.

There are many fsm(finite state machines) in existence. The two most popular used in digital combinational and sequential circuits are

• Melay Machine
• Moore Machine

The main difference between melay and moore is the computation of the next state. In melay machine the output depends on the current state and the input variables. Where as in moore machine the output depends on the current state only. There are also other differences which are hardly highlighted any where.
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Moore Machine

1. More number of states in moore compared to melay for same fsm.
2. States changes after 1 clock cycle. Latency = 1.
3. Synchronous output. Because the states are determined in a process.
4. States are output.

Mealy Machine

Vhdl Code For Serial Adder Using Finite State Machines

1. Less number of states in mealy compared to moore for same fsm.
2. State transition on the same clock cycle. Latency = 0.
3. Asynchronous output.
4. Transition are output.

Parallel Adder

Filed Under: Microcontroller Projects, VHDL

Vhdl Code For Serial Adder Using Finite State Machine Programming